1. Field of the Invention
The present invention relates to a wireless communication receiver circuit of a direct conversion system. In particular, the present invention relates to a wireless communication receiver circuit which has a DC offset canceling function.
2. Description of Related Art
Conventional signal processing systems used in wireless communication for cellular phones or the like include a superheterodyne system. In such a superheterodyne system, a process of downconverting of a reception signal to an intermediate frequency is temporarily required, and thus, the circuit scale is large.
In recent years, as a solution of this problem, a direct conversion system has been developed wherein downconversion into the intermediate frequency is not necessary. However, in the direct conversion system, the output of the DC offset to the next stage is amplified undesirably when a DC offset is present in a reception signal path.
A solution of this problem presents a DC offset canceling method. A receiver circuit carrying out this method has a structure, for example, as shown in FIG. 3. Specifically, the receiver circuit includes a duplexer 101, a first low noise amplifier 102, a band pass filter 103 comprising a SAW (surface acoustic wave) filter, a second low noise amplifier 104, demodulators 105_1, 105_2 comprising mixers, a local oscillator 106, a control logic circuit 107, gain control amplifiers 108_1, 108_2, DC offset canceling circuits 109_1, 109_2, lowpass filters 110_1, 110_2, and a base band block 111. Posterior the demodulators 105_1, 105_2, the circuit is separated into two signal paths for carrying out the signal processes of the in-phase component and the quadrature component separately.
In the receiver circuit having the above structure, the DC offset canceling circuits 109_1, 109_2 respectively connect the input ends to the output ends of the gain control amplifiers 108_1, 108_2. The DC offset canceling circuits 109_1, 109_2 calibrate the DC offset at the input portions of the gain control amplifiers 108_1, 108_2.
The control logic circuit 107, being connected to a local oscillator 106, outputs a frequency control signal for controlling the oscillating frequency. The frequency control signal, being inputted to the local oscillator 106, defines the oscillating frequency in the local oscillator 106. At the time of starting the DC offset canceling operation, the control logic circuit 107 outputs a DC offset canceling signal. The DC offset canceling signal is inputted to the DC offset canceling circuits 109_1, 109_2, and the DC offset canceling operation by the DC offset canceling circuits 109_1, 109_2 starts.
FIG. 4 shows a specific example of a DC offset canceling circuit disclosed in Japanese Laid-Open Patent Publication No. 2001-211098. As shown in FIG. 4, in the DC offset canceling circuit 109_1, the DC offset component at the output of the gain control amplifier 108_1 is read and digitalized by an AD converter 401, and inputted to a control circuit 402. Thereafter, based on a digital signal corresponding to the inputted DC offset component, the control circuit 402 outputs a calibration signal to the DA converter 403 as a digital signal for canceling the DC offset. The DA converter 403 converts the inputted calibration signal to an analog signal and outputs to the gain control amplifier 108_1. Thus, the DC offset voltage at the output of the gain control amplifier 108_1 is calibrated, and the DC offset is cancelled.
As shown in FIG. 4, at the time of canceling the DC offset, the DC offset is detected at the output portion of the gain control amplifier 108_1. When a reception signal is present at the time of detecting the DC offset, an AC voltage is superimposed on the offset potion of the DC voltage. Therefore, during the DC offset canceling operation period, it is not possible to detect only the DC offset if the reception signal is present. Therefore, the accuracy in the DC offset canceling operation is low.